# KiCad BOM and CPL for JLCPCB: Export Files That Pass Review *Published: 2026-09-29 | Author: Jason Ratzlaff* To get a KiCad BOM and CPL for JLCPCB that passes review, you need three things: a Gerber and drill zip plotted with JLCPCB’s recommended settings, a BOM whose columns are Comment, Designator, Footprint and an LCSC part number, and a CPL whose columns are Designator, Mid X, Mid Y, Rotation and Layer in millimetres. Most failed orders come down to renamed columns, missing LCSC numbers or rotation offsets, and all three can be fixed inside KiCad before you ever upload. I design boards end to end, from schematic to firmware, and most of my prototypes go through JLCPCB’s assembly service. The export itself is quick. What costs days is a board that comes back with a diode backwards, or an order that sits in review while an engineer emails you about a part that does not match its footprint. This guide is the process I use so the files are right the first time, with every setting checked against KiCad’s and JLCPCB’s own documentation. ![Workflow diagram: KiCad schematic and PCB produce BOM.csv, CPL.csv and a Gerber zip, which JLCPCB checks as BOM match, placement preview and DFM review](https://www.parkktech.com/wp-content/uploads/2026/09/kicad-jlcpcb-export-workflow.png)Three files leave KiCad. Each one maps to a check on JLCPCB’s side, so a problem in review always points back to one file.How to Export KiCad for JLCPCB: The Three Files ----------------------------------------------- A bare PCB order needs only Gerbers and drill files, plotted from the PCB Editor under File, Fabrication Outputs. An assembly order adds two spreadsheets: the bill of materials, which tells JLCPCB *what* to place, and the component placement list (CPL, also called the centroid or pick-and-place file), which tells the machine *where* and *at what angle*. JLCPCB matches the two by reference designator, so R12 in the BOM must be R12 in the CPL, with the same capitalisation. FileWhat JLCPCB does with itMade inGerbers + drill (.zip)Fabricates the bare board and runs the DFM checkPCB EditorBOM (.csv)Matches each line to a part in its library by LCSC numberSchematic EditorCPL (.csv)Drives the pick-and-place machine and the placement previewPCB Editor### What JLCPCB’s review actually checks After upload, three separate checks run. The BOM is matched against JLCPCB’s parts library and stock. The CPL is overlaid on your Gerbers so you can confirm every part sits on its pads at the right rotation. Then a human engineer reviews the job and, for assembly, produces a DFM image for you to confirm. You can skip ahead of the engineer by getting the first two right yourself, and that is where the rest of this guide focuses. KiCad Gerber and Drill Settings for JLCPCB ------------------------------------------ JLCPCB publishes a KiCad 9 Gerber guide, and its settings are close to KiCad’s defaults. The ones that matter are below. If your KiCad version shows slightly different labels, the intent is the same. ### Plot settings SettingWhyValueLayers (2-layer)The minimum set for a bare boardF.Cu, B.Cu, F.Mask, B.Mask, F.Silkscreen, B.Silkscreen, Edge.CutsPaste layersRequired for the SMT stencil on assembly ordersF.Paste, B.PasteInner layersMissing inner layers is a silent failure on 4-layer boardsIn1.Cu and up, per your stackupCheck zone fills before plottingStops stale copper pours from shippingOnUse Protel filename extensionsStandard layer extensions the viewer recognisesOnUse extended X2 formatEmbeds layer function metadataOnInclude netlist attributesJLCPCB notes this improves its DFM checksOnCoordinate formatFull precision in millimetres4.6, mmDrill marks / scale / modeAnything else distorts the artworkNone / 1:1 / Filled### Drill file settings Generate Excellon drill files in millimetres with decimal zeros format, absolute origin, and “Use alternate drill mode for oval holes” ticked so slots come out correctly. Leave “PTH and NPTH in single file” unticked; KiCad then writes separate `-PTH.drl` and `-NPTH.drl` files, which is what JLCPCB’s guide shows. Zip the Gerbers and both drill files together, with English-only filenames, and open the zip in JLCPCB’s online Gerber viewer before you go any further. If you script your outputs, `kicad-cli` produces the same files. X2, netlist attributes and Protel extensions are on by default, so you only switch them off with `--no-x2`, `--no-netlist` or `--no-protel-ext`. The CLI plots the board as it was saved, so refill zones (press B in the PCB Editor) and save before running it. Terminal: Gerbers and drill files for a 2-layer JLCPCB assembly order``` kicad-cli pcb export gerbers --output fab/ \ --layers "F.Cu,B.Cu,F.Paste,B.Paste,F.Silkscreen,B.Silkscreen,F.Mask,B.Mask,Edge.Cuts" \ board.kicad_pcb kicad-cli pcb export drill --output fab/ \ --excellon-units mm --excellon-zeros-format decimal \ --excellon-oval-format alternate --excellon-separate-th \ board.kicad_pcb cd fab && zip ../gerbers.zip * ``` JLCPCB BOM File Format from KiCad --------------------------------- JLCPCB’s sample BOM uses four columns: **Comment**, **Designator**, **Footprint** and **JLCPCB Part #**. KiCad’s Symbol Fields Table exports Reference, Qty, Value, Footprint and so on, so the job is to add one field and rename two headers. ### Add an LCSC Part # field to every placed symbol JLCPCB matches parts by their LCSC code, the “C” number on every part page (for example C25804). In the Schematic Editor, open Tools, Edit Symbol Fields Table, add a field named `LCSC Part #` and fill it in for every part you want placed. I put the field in my own symbol libraries so that a 10k 0402 resistor carries its code everywhere it is used, which removes a whole class of matching errors. Without that field, JLCPCB tries to match on value and footprint text. That is how you get “No Part Selected” or a package warning, and how a resistor can be matched to the right value in the wrong size. ### Export and rename the columns On the Export tab, rename Reference to Designator and Value to Comment, keep Footprint, and export the LCSC field with the label `JLCPCB Part #`. Group by value, footprint and LCSC number so each line is one unique part. JLCPCB asks for no more than 200 designators per BOM line and each designator only once in the whole file. The command-line version has one trap worth knowing. The designator list is comma separated inside a comma-separated file, and `kicad-cli` uses no string delimiter by default. Without quotes, “R1,R2,R3” splits across columns and the upload fails with a format error. Add a quote character as the string delimiter and turn off reference ranges so every designator is listed explicitly. Terminal: a JLCPCB-format BOM straight from the schematic``` kicad-cli sch export bom --output BOM.csv \ --fields "Value,Reference,Footprint,LCSC Part #" \ --labels "Comment,Designator,Footprint,JLCPCB Part #" \ --group-by "Value,Footprint,LCSC Part #" \ --string-delimiter '"' --ref-range-delimiter "" \ --exclude-dnp \ board.kicad_sch # BOM.csv "Comment","Designator","Footprint","JLCPCB Part #" "10k","R1,R2,R7","Resistor_SMD:R_0402_1005Metric","Cxxxxx" ``` The part number is a placeholder. Look up your own in the JLCPCB parts library and check its package against your footprint before you paste it in. JLCPCB CPL File: Component Placement from KiCad ----------------------------------------------- The CPL comes from the PCB Editor under File, Fabrication Outputs, Component Placement. JLCPCB’s KiCad guide exports it as CSV, in millimetres, as a single file for both sides, and then renames five headers. KiCad .pos (CSV) as exported ReferenceRef X positionPosX Y positionPosY AngleRot Board sideSide JLCPCB CPL what the upload expects ReferenceDesignator X positionMid X Y positionMid Y AngleRotation Board sideLayer Terminal: CPL export, then rename headers for JLCPCB``` kicad-cli pcb export pos --output CPL.csv \ --format csv --units mm --side both --exclude-dnp \ board.kicad_pcb # KiCad writes: Ref,Val,Package,PosX,PosY,Rot,Side sed -i '1s/.*/Designator,Val,Package,Mid X,Mid Y,Rotation,Layer/' CPL.csv ``` ### Units, origins and bottom-side parts Two settings quietly break placement. First, `kicad-cli` defaults to inches for position files, so always pass `--units mm`. Second, the CPL and the Gerbers must share an origin. If you plotted Gerbers from the absolute origin, do not tick “use drill/place file origin” for the CPL, and the reverse. JLCPCB overlays the CPL on your Gerbers, so a mismatched origin shows every part shifted by the same distance. For double-sided assembly, keep both sides in one file; JLCPCB accepts Top and Bottom (or T and B) in the Layer column. I leave “negate bottom side X” off, because it mirrors X on bottom parts and they would no longer line up with the Gerbers in the viewer. JLCPCB also wants at least 0.2 mm between the coordinates of any two designators, which catches stacked footprints and duplicated parts. JLCPCB Rotation Offset: Why Parts Come Out Sideways --------------------------------------------------- This is the most common JLCPCB assembly problem with KiCad, and it is not a KiCad bug. Every footprint library defines 0 degrees somewhere, and the orientation of a part in its tape is defined by the reel. KiCad’s library follows its own zero-orientation convention; the tape often does not match it. Both ends use the same rotation standard, as JLCPCB puts it, but they start counting from different places. The result is a CPL that says 0 degrees for a part that needs 90, 180 or 270 degrees to land on its pads. ![Illustrative diagram of a SOT-23 part: aligned with its KiCad footprint at 0 degrees, rotated 90 degrees off its pads in the placement view, and aligned again after a +90 degree rotation offset](https://www.parkktech.com/wp-content/uploads/2026/09/jlcpcb-rotation-offset-illustration.png)Illustrative. The CPL angle is correct for your footprint; the offset corrects for how the part sits in the reel.SOT-23 transistors and regulators, SOIC and QFN ICs, polarised capacitors, LEDs and diodes are the usual suspects. For two-terminal parts with no polarity, a 180-degree error does not matter. For everything else, it is a dead board. ### Fix it at the source with offset fields The durable fix is to store the correction on the part, not in a spreadsheet you will regenerate next week. The Fabrication Toolkit plugin reads a symbol or footprint field named `FT Rotation Offset` (it also accepts `Rotation Offset` and `RotOffset`) and adds it to the exported angle. A matching `FT Position Offset` field shifts the centroid for parts whose footprint origin is not the body centre. The toolkit also ships a rotation table (rotations.cf) that corrects most common packages automatically, so you only add fields for the exceptions. The kicad-jlcpcb-tools plugin takes the database route: it adopted the rotation corrections from Matthew Lai’s JLCKicadTools and gives you a Rotation manager to add your own. Either way, once a correction is set it survives every re-export. ### Fix it in the placement preview After upload, JLCPCB’s component placement view shows each part on your board. Zoom in on every polarised part and check pin 1 against the silkscreen marker. You can rotate parts in the tool, but fix the source too, or the same error comes back on the next order. **The silkscreen wins when it disagrees with your CPL.**JLCPCB states that when a pin-1 mark on the silkscreen conflicts with the CPL, it places by the silkscreen. That is a safety net, not a plan: put a clear, unambiguous pin-1 or polarity mark on every polarised footprint so the engineer and the machine agree with you. ![Macro photography of black circuit board](https://images.unsplash.com/photo-1518770660439-4636190af475?ixid=M3w4ODMzNjJ8MHwxfHNlYXJjaHwyfHxlbGVjdHJvbmljJTIwY29tcG9uZW50c3xlbnwxfDB8fHwxNzkwNjY5NTY4fDA&ixlib=rb-4.1.0&w=1520&q=80&fm=jpg&fit=crop&ar=16:9)Photo by [Alexandre Debiève](https://unsplash.com/@alexkixa?utm_source=parkk_blog&utm_medium=referral) on [Unsplash](https://unsplash.com/?utm_source=parkk_blog&utm_medium=referral)JLCPCB Basic vs Extended Parts ------------------------------ JLCPCB’s parts library is split into basic parts, which stay loaded on the machines, and extended parts, which an operator loads by hand for your job. On Economic PCBA that loading carries a per-part fee for each unique extended part. Parts marked “Preferred Extended” are exempt from that fee on Economic orders. The Standard service loads a feeder for every part, basic or extended, at a lower per-part rate but with a larger setup fee. **$8.18**Economic PCBA setup fee*Standard: $25.56 single side* **$3.07**per unique extended part*Economic feeder loading* **0.2 mm**minimum designator spacing*in the CPL* **200**designators per BOM line*maximum* ![Bar chart of JLCPCB assembly fees: setup $8.18 Economic vs $25.56 Standard, stencil $1.53 vs $8.21, feeder loading $3.07 per extended part vs $1.53 per part](https://www.parkktech.com/wp-content/uploads/2026/09/jlcpcb-assembly-fees-economic-vs-standard.png)Figures from JLCPCB’s “PCB Assembly Cost” help article, retrieved September 2026. Prices change; the quote page is the source of truth.On a simple board, the extended-part fee can be larger than the setup fee: ten unique extended parts on Economic is ten loading fees. So when there is a choice, I pick passives, common LDOs and small-signal transistors from the basic list and save extended slots for the parts that define the design. The library filter shows the category on every part page. Common JLCPCB BOM and CPL Rejection Reasons ------------------------------------------- JLCPCB publishes a list of the messages its matching page shows. These are the ones I see KiCad users hit most, with the fix on the KiCad side. Message or symptomCause and fixFix in“The uploaded file format is incorrect”Bad formatting, invalid entries or special characters in the filename. Quote the designator column and use plain ASCII filenames.BOM or CPLDesignators in BOM not found in CPLDifferent sets or capitalisation between files. Export both from the same revision with the same DNP exclusion.Both“Repeated Designator”A designator appears twice, or two parts sit closer than 0.2 mm. Re-annotate, run DRC and remove duplicated footprints.Schematic, PCB“No Part Selected”Not enough information to match the line. Add the LCSC Part # field.BOMPackage verification warningThe matched part’s package differs from the BOM. Check the LCSC code against your footprint size.BOM“Shortfall”Not enough stock, or a minimum quantity with attrition. Choose an in-stock alternate or pre-order.BOM“Standard Only”A part needs Standard PCBA but Economic is selected. Switch service or pick an alternate.BOMParts rotated in previewFootprint zero differs from reel orientation. Add a rotation offset field, or fix it in the placement tool and carry it back.Footprint fieldsTwo causes do not show up as messages. Through-hole parts you intend to solder yourself should carry the “Exclude from position files” attribute, or they appear in the CPL. And a board revision with new designators needs both files regenerated: an old CPL with a new BOM is the quickest way to a mismatch. KiCad JLCPCB Plugin: Fabrication Toolkit vs kicad-jlcpcb-tools -------------------------------------------------------------- You can do everything above by hand, but two free plugins remove the renaming step. Both install from KiCad’s Plugin and Content Manager. OptionWhat it producesBest forFabrication Toolkit (bennymeg)Gerbers, BOM, CPL and an IPC netlist in JLCPCB format in one click; reads LCSC fields and FT Rotation/Position Offset fields; excludes DNP; has a CLI. JLCPCB’s own KiCad guide recommends it.Default choicekicad-jlcpcb-tools (Bouni)Gerber zip, BOM and CPL; searches the JLCPCB parts database from inside KiCad; rotation manager; KiCad 7 to 10Choosing parts in KiCadkicad-cli scriptingExactly the commands above, in a Makefile or CI jobRepeatable releasesI use the Fabrication Toolkit for one-off prototypes and a scripted `kicad-cli` pipeline for anything that will be reordered, because the outputs then live next to the design in version control. The toolkit’s own CLI makes that easy to combine: Terminal: Fabrication Toolkit from the command line``` python3 -m plugins.cli -p /myProject/myBoard.kicad_pcb --excludeDNP ``` If you want placement itself to go faster before any of this, I wrote about [getting a KiCad board from chaos to routable](https://www.parkktech.com/kicad-fluxplace-pcb-placement-tool/) with fluxplace. JLCPCB Pre-Order Checklist -------------------------- This is the sequence I run before every assembly order. It is short, and it replaces the back-and-forth with review. 1. **Run ERC and DRC with JLCPCB’s rules.** Load their capability limits into Board Setup for your layer count and copper weight, then clear every error. 2. **Refill zones and save.** Press B, save, and only then plot or script. 3. **Check LCSC numbers.** Every placed part has an LCSC Part # field; every code’s package matches its footprint; note which are extended. 4. **Mark DNP and hand-soldered parts.** Set Do not populate or Exclude from position files so the BOM and CPL agree. 5. **Export Gerbers and drill files.** Include paste layers and every inner copper layer; separate PTH and NPTH files; zip them. 6. **Export BOM and CPL from the same revision.** Millimetres, both sides in one CPL, headers renamed or produced by the plugin. 7. **Open the zip in JLCPCB’s Gerber viewer.** Confirm the outline, drill hits and every layer. 8. **Review the BOM match page.** Resolve every warning rather than clicking past it. 9. **Check every polarised part in the placement preview.** Pin 1 against silkscreen, diode bars, LED polarity, IC orientation. 10. **Feed corrections back into KiCad.** Add rotation offset fields for anything you rotated so the next order is clean. **Fix the design, not the upload.**Every correction made in JLCPCB’s web tools is lost when you reorder or revise the board. Every correction stored as a field on the symbol or footprint is permanent. Frequently Asked Questions -------------------------- How do I generate a CPL file in KiCad?In the PCB Editor, choose File, Fabrication Outputs, Component Placement (.pos). Select CSV format, millimetres and a single file for both sides, then rename the headers Ref, PosX, PosY, Rot and Side to Designator, Mid X, Mid Y, Rotation and Layer. The Fabrication Toolkit plugin produces the same file already in JLCPCB format. What is the JLCPCB BOM file format?JLCPCB’s sample BOM has four columns: Comment, Designator, Footprint and JLCPCB Part #. Each line is one unique part, with all of its designators in one cell. Keep each designator to one appearance in the file and no more than 200 designators per line. How do I use the JLCPCB KiCad plugin?Install the Fabrication Toolkit from KiCad’s Plugin and Content Manager, add an LCSC Part # field to your symbols, then click the toolkit’s button in the PCB Editor. It writes the Gerber zip, BOM and CPL in JLCPCB’s format into an output folder in your project, ready to upload. What is the difference between JLCPCB basic and extended parts?Basic parts stay loaded on JLCPCB’s machines, while extended parts are loaded by hand for your job. On Economic PCBA each unique extended part adds a feeder loading fee, listed at $3.07 in September 2026, unless it is marked Preferred Extended. Standard PCBA charges a loading fee for every part. Why are my components rotated wrong on JLCPCB?KiCad footprints and component reels define 0 degrees differently, so the CPL angle is correct for your footprint but not for the tape. Add a rotation offset field (for example FT Rotation Offset for the Fabrication Toolkit) to the affected parts, or correct them in JLCPCB’s placement preview and then carry the fix back into KiCad. How do I upload KiCad files to JLCPCB?Zip the Gerbers and drill files and upload the zip on JLCPCB’s order page, then enable PCB Assembly. Upload the BOM and CPL when prompted, resolve any matching warnings, check the placement preview and confirm the order. An engineer reviews it before production. Why is JLCPCB assembly so expensive for a small board?The fixed fees dominate small runs: a setup fee, a stencil fee and a loading fee for each unique extended part on Economic PCBA. Designing with basic parts where possible is usually the largest saving, since ten extended parts cost ten loading fees regardless of quantity. Sources: [JLCPCB: How to export BOM and CPL files from KiCad](https://jlcpcb.com/help/article/how-to-generate-the-bom-and-centroid-file-from-kicad), [JLCPCB: Gerber and drill files in KiCad 9](https://jlcpcb.com/help/article/how-to-generate-gerber-and-drill-files-in-kicad-9), [JLCPCB: Common BOM/CPL matching issues](https://jlcpcb.com/help/article/common-bom-and-cpl-matching-issues-and-explanations), [JLCPCB: BOM/CPL preparation recommendations](https://jlcpcb.com/help/article/advice-for-bom-and-cpl-files-preparation), [JLCPCB: PCB assembly cost](https://jlcpcb.com/help/article/pcb-assembly-price), [JLCPCB: PCB assembly FAQs (Part 2)](https://jlcpcb.com/help/article/pcb-assembly-faqs-part-2), [KiCad 9 command-line interface documentation](https://docs.kicad.org/9.0/en/cli/cli.html), [Fabrication Toolkit on GitHub](https://github.com/bennymeg/Fabrication-Toolkit), [kicad-jlcpcb-tools on GitHub](https://github.com/Bouni/kicad-jlcpcb-tools). Need a board built end to end? ------------------------------ I design hardware from schematic and PCB layout through JLCPCB assembly, firmware and edge-AI software. If you want a board that arrives working, or a second pair of eyes on your files before you order, let’s talk. [Start the conversation](https://www.parkktech.com/contact/) --- **Parkk Technology** — Custom Software Development, AI Integration, and Equity Partnerships - Custom Software Development: We build the software your business actually needs — scoped, shipped, supported. - AI Integration for Existing Businesses: Add AI capabilities to what you already have — without rebuilding everything. - Equity Partnership: Considered case by case for validated problems. No fixed package. Contact: https://www.parkktech.com/contact | Author: Jason Ratzlaff, founder of Parkk Technology