4 Layer vs 6 Layer PCB: Controlled Impedance Stackups in KiCad

I design boards end to end, from schematic to the firmware that runs on them, and most of them are ordered from JLCPCB straight out of KiCad. This is how I choose a PCB stackup for controlled-impedance traces. Every specific number comes from a public source you can check: JLCPCB’s published stackup tables, the KiCad documentation and the IPC-2141 design guide.

What Is a PCB Stackup, and Why Does It Set Impedance?

A PCB stackup is the ordered list of copper layers and the insulating material between them: which layer is signal, which is plane, and exactly how thick each dielectric is. The characteristic impedance of a trace depends on four things: trace width, copper thickness, the distance to the nearest reference plane, and the dielectric constant (Er) of the material in between. You draw only the width; the stackup sets the rest.

PCB stackup core vs prepreg

A multilayer board is built from two kinds of dielectric. A core is a rigid, fully cured laminate that arrives from the material supplier with copper already bonded to both faces; its thickness is tightly controlled. Prepreg is glass cloth impregnated with partially cured resin. It is the glue: sheets of it sit between cores and the outer copper foil, and the press cycle melts and cures it. The glass style number (7628, 2116, 3313, 1080) sets its thickness and dielectric constant.

On a standard 4-layer board, the outer copper sits on prepreg and the two inner layers are the faces of a single core. That means the top-layer microstrip impedance is set by the prepreg thickness, not by the overall 1.6 mm board thickness.

What controlled impedance means on a fab order

Ticking “impedance control” on an order asks the fab to hold the finished impedance of the specified traces within a tolerance, which JLCPCB lists as 10% on its FR-4 service. Your part is to design to the fab’s stackup and tell them which traces are controlled, to what target. The general method, including test coupons and the closed-form equations most calculators start from, is documented in IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards.

Reference Planes: The Part of the Stackup That Matters Most

Every signal is a loop. The current that leaves on a trace comes back on the nearest plane, and at high frequency it returns directly underneath the trace, because that path has the lowest inductance. The trace and its reference plane together form the transmission line.

Three rules follow from that, and they matter more than the layer count:

• Never route a controlled trace across a split or slot in its reference plane. The return current has to detour around the gap, the loop grows, impedance jumps at the gap and the loop radiates.
• When a trace changes layers, give the return current a path too. If the reference changes from one ground plane to another, place a ground via next to the signal via. Referencing a power plane instead leaves only a decoupling capacitor as the bridge.
• Keep the reference plane close. Thin dielectric means a narrower trace, tighter fields and less crosstalk.

Best 4 Layer PCB Stackup for Controlled Impedance

For almost every 4-layer board I build, the arrangement is Signal / Ground / Power / Signal, or better, Signal / Ground / Ground / Signal with power poured on the outer layers where there is room. Layer 2 is solid ground under the top layer, where parts and controlled traces live; keep layer 3 ground too if power allows, since the bottom layer references it.

The 4-layer weakness is structural: the two inner planes are separated by a thick core (around 1 mm on a 1.6 mm board), so layer 2 and layer 3 give you almost no plane-to-plane capacitance, and only the two outer layers are good places for controlled traces.

4 layer PCB stackup at JLCPCB

JLCPCB publishes a fixed set of impedance stackups, and designing to one of them is the simplest way to get a predictable result. These are the 1.6 mm single-prepreg options, as listed on its controlled impedance page (fetched September 28, 2026):

Outer copper is listed at 0.035 mm (1 oz) and inner copper at 0.0152 mm; JLCPCB gives the core dielectric constant as 4.6 and the solder mask as 3.8.

Choosing between the 4-layer options

Thin outer prepreg (3313 or 1080) is my default for boards with controlled traces. The 50-ohm trace width lands near what fine-pitch parts can actually connect to, and the tighter coupling to layer 2 keeps fields contained. Thick 7628 prepreg gives a wide 50-ohm trace, which is easy to fabricate but hard to neck down into a small pad without an impedance step.

6 Layer PCB Stackup Options

Six layers give you two more copper layers, but the real gain is where they sit. The standard 6-layer approach is Signal / Ground / Signal / Signal / Power / Signal or, the one I prefer when impedance matters, Signal / Ground / Signal / Ground / Power / Signal. There, layer 3 is a true stripline between two grounds, so it neither radiates nor picks up much.

Source: JLCPCB controlled impedance stackups, 1.6 mm, 1 oz outer copper, fetched September 28, 2026.

Best 6 layer PCB stackup for EMI

Look at the outer prepreg column. JLC06161H-3313 has the same 0.0994 mm, Er 4.1 outer dielectric as the 4-layer JLC04161H-3313, so a 50-ohm top-layer microstrip is the same width on both. Six layers do not change outer-layer impedance; they add a buried signal layer and room for a power plane without losing a ground under either outer layer.

The catch is the thick cores. On JLC06161H-3313, layer 3 sits 0.55 mm from layer 2 but only about 0.11 mm from layer 4, so a trace on layer 3 references layer 4 far more strongly than layer 2. That asymmetric stripline is fine only if layer 4 is solid ground. My EMI rule: every signal layer gets an adjacent solid ground, and the fastest signals go where that ground is closest.

4 Layer vs 6 Layer PCB: What the Extra Layers Buy

My decision question: can every controlled or fast trace have solid ground directly under it, with no crossings, on four layers? If yes, four layers is enough. If I am cutting the ground plane to route power, six layers pay for themselves.

4 layer vs 6 layer PCB cost

Six layers cost more: more material, another lamination step and more drilling time. How much more depends heavily on quantity, size and options, and JLCPCB’s public pricing is promotion-driven. On September 28, 2026, its 6-layer PCB page advertised 5 pieces “from $2” alongside a separate 6-layer coupon, and its home page listed FR-4 boards of 1 to 32 layers “from $2.00 / 5 pcs” with free plated-over-filled vias (POFV) on 6+ layers. Those are promotional headline figures, not a like-for-like comparison. I quote the same board twice, as 4 and 6 layers with impedance control selected, and compare.

How to Calculate a 50 Ohm Trace

There are two ways to size a controlled trace: a closed-form approximation for a first estimate, and a field solver (or the fab’s own calculator) for the number you actually route.

Microstrip

A microstrip is a trace on an outer layer over a reference plane, with air (and solder mask) above it. The classic IPC-2141 approximation is:

Z0 = 87 / sqrt(Er + 1.41) * ln( 5.98 * h / (0.8 * w + t) )

Rearranged for width:
w = ( 5.98 * h / exp( Z0 * sqrt(Er + 1.41) / 87 ) - t ) / 0.8

It is only a guide, commonly quoted as reasonable for w/h between about 0.1 and 2.0, and it ignores solder mask and frequency effects. Plugging in JLCPCB’s published prepreg thicknesses and dielectric constants for 1 oz outer copper gives these starting widths:

Two things stand out. First, the 7628 build needs a trace about 0.35 mm wide, wider than the pads of many small components, so every pad transition becomes a small impedance discontinuity. Second, the 1080 build needs about 0.108 mm (4.3 mil), which is still comfortably above JLCPCB’s listed 3.5 mil minimum trace width but leaves less room for etch variation.

Coplanar waveguide with ground (GCPW)

A grounded coplanar waveguide is a microstrip with ground copper on the same layer on both sides, separated by a controlled gap, and tied to the plane below with rows of vias. The side grounds let the trace be narrower for the same impedance and keep more of the field contained.

The trade-off is sensitivity: over-etching shifts impedance through both the width and the gap. If the gap is large compared with the dielectric height, the line behaves like a microstrip anyway. I use GCPW for a narrow trace on thick dielectric or a line running near other circuitry; for a short run on thin prepreg, a microstrip with the pour pulled back is simpler.

Using the KiCad impedance calculator

KiCad ships a standalone PCB Calculator, and its TransLine tool models microstrip, coplanar waveguide, coplanar waveguide with ground plane, stripline, coupled microstrip (for differential pairs) and several other line types. You enter the substrate parameters (Er, loss tangent, dielectric height, copper thickness), then either analyse a given width or synthesize the width for a target impedance.

Put JLCPCB’s numbers in, not generic FR-4 defaults. Feed it the total board thickness instead of the prepreg and it gives a confident, wrong answer.

The JLCPCB impedance calculator

For the final width, I use the fab’s own JLCPCB impedance calculator, because it models its stackups including the solder mask coating it publishes (1.2 mil over substrate, 0.6 mil over trace, Er 3.8). I then route to that width in KiCad and name the stackup on the order. If the two differ slightly, the fab’s number wins.

Setting Up the PCB Stackup in KiCad

This is the sequence I follow on every controlled-impedance board.

1. Pick the fab stackup first. Choose the JLCPCB stackup name that matches the board thickness and copper weight, and write it into the board’s fabrication notes.
2. Enter it in Board Setup. In the PCB Editor, open Board Setup, then Board Stackup, then Physical Stackup. Set the copper layer count and type each dielectric’s thickness and dielectric constant from the fab table.
3. Size the traces. Calculate widths (and gaps for GCPW or differential pairs) with the TransLine tool, then confirm them in the fab’s calculator.
4. Make a net class per impedance. Create net classes such as “50R_SE” with the computed track width and clearance, and assign the controlled nets to them so routing and DRC enforce the width.
5. Document it on the board. Use KiCad’s Add Stackup Table and Add Board Characteristics tools to place both tables on a documentation layer so the fabrication drawing states the stackup and which nets are controlled.

Per the KiCad PCB Editor manual, layer thicknesses from this page also feed the 3D export and via-aware net length calculations.

Via Stitching and Via Fencing

What is via stitching?

Via stitching is placing ground vias that tie copper on different layers together: top-layer ground pour to the layer 2 plane, layer 2 to layer 3, and so on. Without it, a top-layer pour connects only where pads touch it, leaving islands and floating fingers. Stitching makes all the ground copper on the board behave as one low-impedance ground.

Why via stitching?

• Return paths across layer changes. A ground via beside every signal via that changes reference plane keeps the return loop small.
• Defined pour edges. A row of vias along the edge of a pour, and around the board outline, keeps the pour edge tied to the plane instead of floating.
• Isolation. A via fence between a noisy section and a sensitive one reduces coupling through the dielectric.

Via fence spacing

A via fence alongside a GCPW or around a sensitive section works only if the gaps between vias are small compared with the wavelength of the highest frequency content on the board. The common rule of thumb is spacing no larger than about one-twentieth of the guided wavelength in the dielectric; some designers use one-tenth as a looser limit. The via fence overview and EDN’s via spacing on high-performance PCBs are good starting points. For digital signals, the edge rate sets the frequency that matters, not the clock.

On a GCPW I keep fence vias a consistent distance from the gap edge, on both sides, for the full run.

How to do via stitching in KiCad

KiCad supports this directly. The PCB Editor has a tool to place free-standing vias, and the manual notes that free vias “may be useful for via stitching, via shielding, thermal design”. Set the via’s net to GND. For long rows, place one via and use Create Array (Ctrl+T) to repeat it at a fixed pitch. KiCad normally updates via nets automatically from the connected copper; for stitching vias you can turn that off per via with the “automatically update via nets” option in via properties so they keep their GND net. For filling large pours, the open-source kicad-action-scripts collection includes a via stitching plugin.

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